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| AFBR-5905Z/5905AZ ATM Multimode Fiber Transceivers in 2 x 5 Package Style Agilent AFBR-5905Z/5905AZ ATM Multimode Fiber Transceivers in 2 x 5 Package Style Data Sheet Features Data Sheet * Multisourced 2 x 5 pack with MT-RJ receptacle * Single +3.3 V power sup Description Transmitter Sections * Wave solder and aqueo The AFBR-5905Z family of The transmitter section of the process compatibility transceivers from Agilent AFBR-5905Z utilizes a 1300 * Full compliance with AT provide the system designer Features InGaAsP LED. This LED is nm UNI SONET OC-3 multim Description with products to implement a packaged in the optical physical layer specifica The AFBR-5905Z family of transceivers from Avago pro* Multisourced 2 x 5 portion style with MT-RJ range of solutions for subassembly package of the * RoHS compliant vide the system designer with products fiber SONET a multimode to implement OC-3 receptacle transmitter section. It is driven * Receiver output squelch range of solutions for multimode fiber SONET OC-3 (SDH (SDH STM-1) physical layers* Single +3.3 V power supplyIC which by a custom silicon enabled STM-1) physical layers for ATM and other services.services. for ATM and other These converts differential PECL * Wave solder and aqueous wash process compatibility Applications transceivers are all supplied in the new industry standard logic signals, ECL referenced These transceivers are 2 x 5 DIP style with a MT-RJ fiber connector interface. all * Full(shifted) towith ATMV supply, SONET OC-3 compliance a +3.3 Forum UNI * supplied in the new industry multimode fiber physical layer specification Multimode fiber ATM ba links into an analog LED drive ATM 2 km Backbone Links standard 2 x 5 DIP style with RoHS compliant current. * * Multimode fiber ATM w a MT-RJ fiber connector closet to desktop links The AFBR-5905Z is a 1300 nm product with optical perforinterface. * Receiver output squelch function enabled Receiver Sections mance compliant with the SONET STS-3c (OC-3) Physical ATM physical layer is defined The receiver section of the Ordering Information Layer Interface Specification. This2 km Backbone Links Applications AFBR-5905Z utilizes an in the ATM Forum User-Network Interface (UNI) Speci- nm The AFBR-5905Z is a 1300 * Multimode fiber ATM backbone links The AFBR-5905Z 1300 InGaAs PIN photodiode fication Version 3.0. This document references the ANSI product with optical product is available fo coupled to ATM wiring closet to T1E1.2 specification for the performance interface for with * Multimode fiber a custom silicon desktop links details of the compliant 2 production orders thro transimpedance preamplifier km multimode fiber backbone links. The STS-3c (OC-3) the SONET ATM 100 Mb/sAgilent Component Fie Ordering Information IC. It is packaged in the 125 MBd Physical Layer interface is Layer Interface Physical best implemented Offices and Authorized optical subassembly portion of with the AFBR- 5903Z family of FDDI Transceivers which for producSpecification. This physical The AFBR-5905Z 1300 nm product is available Distributors world wid the through the are specified for use in this 4B/5B encoded physical layer tion ordersreceiver. Avago Component Field Sales Oflayer is defined in the ATM AFBR-5905Z = 0C to per the FDDI PMD standard. Forum User-Network Interface and Authorized Distributors world wide. fices This PIN/preamplifier combinaAFBR-5905AZ = -40 (UNI) Specification Version 3.0.AFBR-5905Z = 0C to +70Ccustom tion is coupled to a +85C. Transmitter Sections This document references the quantizer IC which provides AFBR-5905AZ pulse shaping for the ANSI T1E1.2 specification the final = -40C to +85C. The transmitter section of the AFBR-5905Z utilizes a 1300 for logic output and the Signal nm InGaAsP LED. This LED isthe details of the interface for packaged in the optical sub2 km multimode driven Detect function. The Data assembly portion of the transmitter section. It is fiber by backbone links. output is differential. The a custom silicon IC which converts differential PECL logic Signal Detect output is singlesignals, ECL referenced (shifted) to a +3.3 V supply, into an The ATM 100 Mb/s-125 MBd analog LED drive current. Physical Layer interface is best ended. Both Data and Signal Detect outputs are PECL implemented with the AFBRcompatible, ECL referenced 5903Z family of FDDI (shifted) to a 3.3 V power Transceivers which are specified for use in this 4B/5B supply. The receiver outputs, Data Out and Data Out Bar, encoded physical layer per the FDDI PMD standard. Receiver Sections 2 x 5 DIP. The low profile of the Avago transceiver design The receiver section of the AFBR-5905Z utilizes an InGaAs complies with the maximum height allowed for the MT-RJ PIN photodiode coupled to a custom silicon transimpedconnector over entire length of the package. ance squelched at Signalpackaged in this optical subpreamplifier IC. It is Detect the package outline and pin theelectrical and optical are assembly portion is, when the This out are compliant with the of the receiver. PIN/preamplifier Deassert. That subassemblies to ensure assembly The optical subassemblies utilize a high-volumehigh combination is coupled to a custom quantizer IC which light input power decreases to multisource definition oftogether with low-costto external EMI result the 2 immunity lens elements which process provides the final pulse shapingthe the x 5 DIP. The low profile of the fields. logic output and a typical -38 dBm or less, for in a cost-effective building block. the Signal Detect function. The Data output is differenSignal Detect Deasserts, i.e. the Agilent transceiver design The outer housing is tial. The DetectDetect output is singleended. Both Datathe The electrical subassembly consists of a high volume mulSignal Signal output goes to a complies with maximum electrically conductive and is tilayer printed and Signal Detect outputs are PECL compatible, ECL ref- for the MT-RJ circuit board on which the IC and various PECL low state. This forces height allowed at reciever signal ground erenced (shifted) to a 3.3 V power supply. The receiver the entire the receiver outputs, Data Out connector over surface-mounted passive circuit elements are attached. potential. The MT-RJ ports is outputs, Data OutBar to goOut Bar, are squelched at Sigand Data Out and Data to length of the package. receiver section includes filled nonconductivethe The molded of an internal shield for nal Detect Deassert. That is, when the light input power steady PECL levels High and electrical The optical subassemblies and optical subassemblies tomechanical implastic to provide ensure high decreases to a typical -38 dBm or less, the Signal Detect Low respectively. munity to external strength and electrical EMI fields. utilize a high-volume assembly Deasserts, i.e. the Signal Detect output goes to a PECL low process together low-cost of Package forces the receiver outputs, Data Out and Data with outer housingisolation. The solder posts is at reThe is electrically conductive and state. This lens elements which result in a the Agilent design are isolated ciever signal ground potential. The MT-RJ ports is molded Out Bar to go to steady PECL levels High and Low respecThe overall package concept cost-effective building block. from the internal circuit of the of filled nonconductive plastic to provide mechanical tively. Agilent transceiver for the transceiver. The electrical subassemblyand electrical isolation. The solder posts of the strength consists of three basic consists of a high Avago design are isolated from the internal circuit to the volume The transceiver is attached of Package elements; the two optical multilayer printedtransceiver. circuit a printed circuit board with subassemblies, an concept for the Avago transceiver electrical The overall package board on which the ten signal pins and the subassembly, and the housing two optical subas- the IC and consists of three basic elements; the The transceiver is attached to a printedwhich board with various surface-mounted two solder posts circuit exit as illustrated in thesubassembly, and the housing as block semblies, an electrical the ten signal pins and the two solder posts which exit the the housing. The diagram in Figure diagram in Figurepassive circuit elements are housing.bottom of the posts provide the illustrated in the block1. 1. bottom of the The two solder attached. two solder posts provide the The package outline drawing primary mechanical strength to withstand the loads imprimary mechanical strength to The package outline drawing and pin out are shown section includes The receiver in and pin out are shown in withstand the loads imposed Figures 2 and 3. The details of this package outline and shield posed on the transceiver by mating with the MT-RJ conpin for the Figures 2 and 3. The details of an internal nectored fiber cables. the transceiver by mating on out are compliant with the multisource definition of the with the MT-RJ connectored fiber cables. RX SUPPLY DATA OUT DATA OUT SIGNAL DETECT DATA IN DATA IN LED DRIVER IC QUANTIZER IC RX GROUND TX GROUND PIN PHOTODIODE PRE-AMPLIFIER SUBASSEMBLY MT-RJ RECEPTACLE LED OPTICAL SUBASSEMBLY TX SUPPLY Figure 1. Block Diagram. 2 13.97 (0.55) MIN. 5.15 (0.20) (PCB to OVERALL RECEPTACLE CENTER LINE) FRONT VIEW 4.5 0.2 (0.177 0.008) (PCB to OPTICS CENTER LINE) Case temperature measurement point 13.59 (0.535) MAX. 9.6 (0.378) MAX. TOP VIEW 10.16 (0.4) Pin 1 7.59 (0.299) 8.6 (0.339) 12 (0.472) 1.778 (0.07) O1.5 (0.059) 17.778 (0.7) 7.112 (0.28) +0 -0.2 (+000) (0.024) (-008) O 0.61 49.56 (1.951) REF. 37.56 (1.479) MAX. 9.8 (0.386) MAX. 9.3 (0.366) MAX. SIDE VIEW 3.3 (0.13) O 1.07 (0.042) DIMENSIONS IN MILLIMETERS (INCHES) NOTES: 1. THIS PAGE DESCRIBES THE MAXIMUM PACKAGE OUTLINE, MOUNTING STUDS, PINS AND THEIR RELATIONSHIPS TO EACH OTHER. 2. TOLERANCED TO ACCOMMODATE ROUND OR RECTANGULAR LEADS. 3. ALL 12 PINS AND POSTS ARE TO BE TREATED AS A SINGLE PATTERN. 4. THE MT-RJ HAS A 750 m FIBER SPACING. 5. THE MT-RJ ALIGNMENT PINS ARE IN THE MODULE. 6. FOR SM MODULES, THE FERRULE WILL BE PC POLISHED (NOT ANGLED). 7. SEE MT-RJ TRANSCEIVER PIN OUT DIAGRAM FOR DETAILS. Figure 2. Package Outline Drawing 33 RX TX Mounting Studs/ Solder Posts Top View RECEIVER SIGNAL GROUND RECEIVER POWER SUPPLY SIGNAL DETECT RECEIVER DATA OUT BAR RECEIVER DATA OUT o o o o o 1 2 3 4 5 10 o 9o 8o 7o o 6 TRANSMITTER DATA IN BAR TRANSMITTER DATA IN TRANSMITTER DISABLE (LASER BASED PRODUCTS ONLY) TRANSMITTER SIGNAL GROUND TRANSMITTER POWER SUPPLY Figure 3. Pin Out Diagram. Pin Descriptions: No internal terminations are based products connect this provided. See recommended pin to +3.3 V TTL logic high Pin 1 Receiver Signal Ground VEE RX: the circuit schematic. Pin 6 Transmitter Power Supply VCC TX: module. To Directly connect this pin to "1" to disable Provide +3.3 V dc via the recommended transmitter power Directly connect this pin to the receiver ground plane. receiver ground plane. enable module connect to TTL Pin 5 Receiver Data Out RD+: supply filter circuit. Locate the power supply filter circuit logic low "0". Pin 2 2 Receiver Power Supply VCC Pin Receiver Power Supply VCC RX: as close are No internal terminations as possible to the VCC TX pin. Provide +3.3 V dc via the recommended receiver power RX: Pin 9 Transmitter provided. See recommended Signal Ground VEE TX: Data In TD+: Pin 7 Transmitter supply filter circuit.dc via the power supply filter circuit Locate the Provide +3.3 V circuit schematic. No internal terminations are Directly connect this pin to the transmitter ground plane. as close as possible to the VCC RX pin. recommended receiver power provided. See recommended Pin 6 Transmitter Power8 Transmitter Disable TDIS: supply filter SD: Pin Supply Pin 3 Signal Detectcircuit. Locate circuit schematic. V the power supply levels to the receiverCC TX: in a logic filter circuit No internal connection. Optional feature for laser based Normal optical input result Pin 10 Transmitter Data In Bar TD-: as close as possible to levels to via the "1" output. Low optical inputthe VCC theProvideresult in dcproducts only. For laser based products connect this pin receiver +3.3 V to +3.3 V high "1" to disable module. are aRX pin. fault condition indicated by a logic "0"recommended transmitter TTL logicNo internal terminationsTo enable output. This Sigpower supply filter circuit. provided. See recommended module connect to TTL logic low "0". nal Detect output can be used to drive a PECL input on Pin 3 Signal Detect SD: Locate the power supply filter circuit schematic. an upstream circuit, such as Signal Detect input or Loss of Normal optical input levels to circuit as close asPin 9 Transmitter Data In TD+: possible to Signal-bar. Mounting Studs/Solder Posts the receiver result in a logic the VCC TX pin. No internal terminations are provided. See recommended Pin 4 Receiver Data Out Bar RD-: circuit schematic. The mounting studs are "1" output. Pin 7 Transmitter Ground No internal terminations are provided. See recommended Signal 10 Transmitter Data In Bar TD-:for transceiver provided Low optical input levels to the Pin VEE TX: circuit schematic. in a fault mechanical attachment to the receiver result No internal terminations are provided. See recommended Directly connect this pin to the circuit board. It is condition indicated by Pin 5 Receiver Data Out RD+: a logic circuit schematic. transmitter ground plane. recommended that the holes in "0" output. No internal terminations are provided. See recommended the circuit board be connected Mounting circuit schematic. Pin 8 Transmitter Disable TDIS: Studs/Solder Posts ground. This Signal Detect output can to chassis be used to drive a PECL input No internal connection. The mounting studs are provided for transceiver mechanion an upstream circuit, such cal attachment to the circuit board. It is recommended Optional feature for laser as Signal Detect input or Loss that the laser based products only. Forholes in the circuit board be connected to chassis of Signal-bar. ground. Pin Descriptions: Pin 1 Receiver Signal Ground VEE RX: Pin 4 Receiver Data Out Bar RD-: 44 Application Information The Applications Engineering group is available to assist plication Information 125 m fiber cables only. The you with the technical understanding and design tradearea under the curves e Applications Engineering offs associated with these transceivers. You can contact represents the remaining oup is available to assist your Avago sales representative. TheOPB them through you folat any link length, which is th the technical underlowing information is provided to answer some of the available for overcoming nonanding and design trade-offs most common questions about the use of these parts. fiber cable related losses. sociated with these transivers. You can contactOptical Power BudgetLED technology has Agilent versus Link Length Transceiver them rough your Agilent sales produced 1300 nm LED Optical Power Budget (OPB) is the available optical power presentative. devices with lower aging for a fiber optic link to accommodate fiber cable losses plus characteristics e following information in-line connectors, splices, than normally losses due to is optical switches, associated with these ovided to answer provide margin for link aging and unplanned losses and to some of technologies in the e most common to cable plant reconfiguration or repair. industry. due questions The industry convention is 1.5 out the use of these parts. dB aging for 1300 nm LEDs. Figure 4 illustrates the predicted OPB associated with the nsceiver Optical Power Budget transceiver specified inThe data sheet at the Beginning this rsus Link Length Life (BOL). These curves represent the attenuation and 1300 nm Agilent LEDs are of dispersion losses associated with tical Power chromatic(OPB) is Budget plus modal specified to experience less the 62.5/125 mfor 50/ 125 m fiber cables only. The area and than 1 dB of aging over normal e available optical power commercial equipment mission under fiber optic link tothe curves represents the remaining OPB at any link length, which is available for overcoming nonfiber cable commodate fiber cable losses life periods. Contact your Agilent sales representative for related losses. us losses due to in-line Avago LED technology has produced 1300 additional details. nm LED devices with lower aging characteristics than nornnectors, splices, optical mally associated with these technologies in the industry. itches, and to provide Figure 4 was generated for the The industry argin for link aging andconvention is 1.5nm aging for 1300 nm LEDs. 1300 dB transceivers with a The 1300 to cable LEDs are specifiedoptic link model nm Avago Agilent fiber to experience less planned losses due than 1 or repair. containing the current industry ant reconfigurationdB of aging over normal commercial equipment mission life periods. Contact your Avago sales representaconventions for fiber cable gure 4 illustrates the pretive for additional details. cted OPB associated with the specifications and the draft ANSI T1E1.2. These optical ansceiver specified in this parameters are reflected in the ta sheet at the Beginning of guaranteed performance of the fe (BOL). These curves transceiver specifications in present the attenuation and this data sheet. This same romatic plus modal model has been used spersion losses associated th the 62.5/125 m and 50/ Figure 4 was generated for the 1300 nm transceivers with extensively in the ANSI and a Avago fiber optic link model containing the current inIEEE committees, including the dustry conventions for fiber cable specifications and the ANSI T1E1.2 committee, to draft ANSI T1E1.2. These optical parameters are reflected establish the optical in the guaranteed performance of the transceiver specifiperformance requirements for cations in this data sheet. This same model has been used various fiber optic interface extensively in the ANSI and IEEE committees, including standards. The cable the ANSI T1E1.2 committee, to establish the optical perparameters used come from formance requirements for various fiber optic interface the ISO/IEC JTC1/SC 25/WG3 standards. The cable parameters used come from the ISO/ Generic Cabling for Customer IEC JTC1/SC 25/WG3 Generic Cabling for Customer PremPremises per DIS 11801 docuises per DIS 11801 document and the EIA/TIA-568-A Comment and the EIA/TIA-568-A mercial Building Telecommunications Cabling Standard Commercial Building per SP-2840. Telecommunications Cabling Standard per SP-2840. 12 HFBR-5905, 62.5/125 m 10 OPTICAL POWER BUDGET (dB) 8 6 4 HFBR-5905 50/125 m 2 0. 3 0 0.5 1.0 1.5 2.0 2.5 FIBER OPTIC CABLE LENGTH (km) Figure 4. Typical Optical Power Budget at BOL versus Fiber Optic Cable Length. 5 Transceiver Signaling Operating Rate Range and BER Performance For purposes of definition, the symbol (Baud) rate, also called signaling rate, is the reciprocal of the symbol time. Data rate (bits/sec) is the symbol rate divided by the enx 10-2 coding factor used to encode the data 1 (symbols/bit). Transceiver Signaling Operating WhenRange and155 Mb/s SONET OC-3 applications the Rate used in BER Performance Agilent recommends that performance of the 1300 nm transceivers,1 xAFBR-5905 is Recommended Handling Precautions 10-3 normal static precautions be For purposes of definition, the guaranteed to the full conditions listed in product specitaken normal static precautions be symbol (Baud) rate, also called 1 x 10-4 Avago recommends thatin the handling and fication tables. The transceivers may be used for other ap- HFBR-5905 SERIES assembly of these transceivers signaling rate, is the reciprocal taken in the handling and assembly of these transceiv1 x 10-5 plications at signaling rates different than 155 Mb/s with to prevent damage which electroof the symbol time. Data rate 1 x 10-6 ers to prevent damage which may be induced bymay CENTER OF SYMBOL some variation in the link optical power budget. Figure 1 x 10-7 be The AFBR-5905Z series of transceiv(bits/sec) is the symbol rate static discharge (ESD). induced by electrostatic 1 x 10-8 5 gives an indication of the typical performance of these divided by the encoding factor 1 x 10-9 ers meet MIL-STD- discharge (ESD). Class 2 products. 883C Method 3015.4 1 x 10-10 products at different rates. The AFBR-5905Z series of used to encode the data 1 x 10-11 Care should be used to avoid shorting the receiver data or 1 x 10-12 transceivers meet MIL-STD(symbols/bit). These transceivers can also be used for applications which -2 signal detect outputs directly to ground without proper -6 0 4 -4 2 883C Method 3015.4 Class 2 require different Bit Error Rate (BER) performance. Figure OPTICAL POWER - dB current limiting impedance. When used in 155 Mb/s RELATIVE INPUT products. 6 illustrates the typical trade-offthe between link BER and the SONET OC-3 applications CONDITIONS: Solder and Wash Process Compatibilityused to avoid receivers input optical power level. Care should be performance of the 1300 nm 1. 125 MBd 2. PRBS 2 -1 shorting the receiver data process transceivers, AFBR-5905 is The transceivers are delivered with protective or 3. CENTER OF SYMBOL SAMPLING Transceiver Jitter Performance 4. T = +25C signal detect outputs This process guaranteed to the full plugs inserted into the MT-RJ receptacle.directly 5. V = 3.3 V dc INPUT OPTICAL to ground without during conditions listed transceivers The Avago 1300 nmin product are designed 6.to oper- RISE/FALL TIMES = 1.0/2.1 ns. the optical subassemblies properwave solplug protects current limiting acts as a dust specification tables. Figure Table B1 of Relative Receiver ate per the system jitter allocations stated in 6. Bit Error Rate vs. der and aqueous wash processing andimpedance. cover BIT ERROR RATE 7 A CC specification tables are derived from the values in Table B1 of Annex B. They represent the worst case jitter contribution that the transceivers are allowed to make to the overall system jitter without violating the Annex B allocation example. In practice, the typical contribution of the Avago transceivers is well below these maximum allowed Recommended Handling Precautions amounts. Input Optical Power. Annex B of the draft ANSI T1E1.2 Revision 3 standard. The during shipping. These transceiversProcess The transceivers may be used Solder and Wash are compatible with Transceiver case Avago 1300applications at will tolerate the worstJitter Performance nm transmitters either industry standard wave or hand solder processes. for other Compatibility input electrical jitter allowed in Annex The Agilent 1300 nm B without violatsignaling rates different than ing the worst case output optical jitter requirements. designed ContainerThe transceivers are delivered 155 Mb/s with some variation transceivers are Shipping to with protective process plugs The the link optical power will tolerate the worst case system jitter Avago 1300 nm receivers in operate per the The transceiver is inserted into shipping container depackaged in a the MT-RJ input optical jitter allowed in Annex B without violating budget. Figure 5 gives an allocations stated signed to B1 in Table protect receptacle. This process plug it from mechanical and ESD damage the worst case output electrical jitter allowed. TheB of theduring shipment or storage. indication of the typical of Annex jitter draft ANSI protects the optical specifications stated in the products1300 nm transceiver 3 standard. performance of these following T1E1.2 Revision subassemblies during wave at different rates. solder and aqueous wash The Agilent 1300 nm 2.5 Recommended 1 x 10-2 processing and acts as a dust Handling Precau Transceiver Signaling Operating will tolerate the transmitters cover during shipping. Rate Range and BER Performance worst case input electrical 2 Agilent recommends that 1 x 10-3 jitter allowed in These transceivers normal static precautions b are compatFor purposes of definition, the Annex B 1.5 taken ible with either industry in the handling and symbol (Baud) without violating the 1worst rate, also called x 10-4 HFBR-5905 SERIES 1 case reciprocal assembly of standard wave or hand solder these transceiv signaling rate, is theoutput optical jitter 1 x 10-5 requirements. to prevent damage which m 0.5 processes. of the symbol time. Data rate 1 x 10-6 CENTER OF SYMBOL x 10-7 be induced by electrostatic (bits/sec) is the symbol rate The Agilent 1300 nm 1receivers 0 1 x 10-8 Shipping Container discharge (ESD). divided by the encoding factor worst 10-9 1 x case will tolerate the 1 x 10-10 -0.5 The AFBR-5905Z series of The transceiver is packaged in used to encodeinput optical jitter allowed in the data 1 x 10-11 1 x 10-12 transceivers a shipping container designed meet MIL-STD (symbols/bit). Annex B without violating the -1 -6 0 4 -4 -2 2 0 25 50 75 100 125 150 175 200 883C Method 3015.4 Class to protect it from mechanical worst case output electrical SIGNAL RATE (MBd) When used in 155 Mb/s RELATIVE INPUT OPTICAL POWER - dB products. and ESD damage during jitter allowed. SONET OC-3 applications the CONDITIONS: CONDITIONS: shipment or storage. 1. PRBS 2 -1 Care should be used to avo performance ofThe jitter specifications stated the 1300 nm 1. 125 MBd 2. DATA SAMPLED AT CENTER OF DATA SYMBOL. 3. BER = 10 shorting the receiver data o transceivers, AFBR-5905 is in the following 1300 nm 2. PRBS 2 -1 SYMBOL SAMPLING 3. CENTER OF 4. T = +25 C 4. T = +25C signal detect outputs direct 5. V = 3.3 V dc guaranteed to the full transceiver specification tables V dc 5. V = 3.3 6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. 6. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. to ground without proper conditions listed inderived from the values in are product current limiting impedance. Figure 5. Transceiver Relative Optical Power tables. B1 of AnnexFigure 6. Bit Error Rate vs. Relative Receiver specification Table B. They Budget at Constant BER vs. Signaling Rate. Input Optical Power. represent used the worst case jitter The transceivers may be Solder and Wash Process contribution that the Transceiver Jitter Performance for other be applications at Compatibility These transceivers can also transceivers are signaling rates different than allowed to The Agilent 1300 nm used for applications which The transceivers are deliver to the overall system 155 Mb/s with make variation transceivers are designed to require different Bit Error Rate some without violating the with protective process plu jitter in the link operate per the system jitter (BER) performance. Figure 6 optical power inserted into the MT-RJ Annex B an allocation example. In budget. Figure 5 gives allocations stated in Table B1 6 illustrates the typical trade-off receptacle. This process plu practice, the typical indication of the typical of Annex B of the draft ANSI between link BER and the protects the optical contribution of the Agilent performance these products receivers input optical power oftransceivers is wellT1E1.2 Revision 3 standard. subassemblies during wave below at different rates. TRANSCEIVER RELATIVE POWER BUDGET AT CONSTANT BER (dB) 7 BIT ERROR RATE -6 7 A CC A CC The Agilent transceiver Board Layout - Decoupling Circuit, Ground Planes and Board Layout - Holecomplies with the circuit board Pattern contiguous ground plane be It is important to take care in "Common Transceiver Termination Circuits The Avago transceiver complies with the circuit board provided in the circuit board the layout of your circuit Footprint" hole pattern defined directly under transceiver It is important to take care in the layout of your circuitthe"Common Transceiverthe original multisource board to achieve optimum in Footprint" hole pattern defined in the original multisource announcement which defined board to achieve optimum performance to provide a low inductance from these transperformance from these announcement which defined ground for signal the 2 x ceivers. Figure 7 Figure 7 a good example of a schematic return5 package style.2 x 5 packagereproduced in Figtransceivers. provides provides the This drawing is style. This ure 9 with the addition of ANSI Y14.5M compliant dimenfor good exampledecoupling circuit that works well with a a power supply of a schematic current. This recommendation drawing is reproduced in as a guide in the mechanical layout good to be these parts. It is further decoupling that a contiguous for a power supply recommended is in keeping withsioninghigh usedFigure 9 with the addition of of your circuit board. ANSI Y14.5M compliant frequency board ground plane be provided in the circuit board directly un- layout circuit that works well with practices. Figures 7 and 8 der the transceiver tofurther a low inductance ground for these parts. It is provide dimensioning to be used as a show two recommended signal return current. This recommendation is in keeping recommended that a guide in the mechanical layout termination schemes. with good high frequency board layout practices. Figures of your circuit board. 7 and 8 show two recommended termination schemes. Board Layout - Decoupling Circuit, Ground Planes and Termination Circuits Board Layout - Hole Pattern PHY DEVICE VCC (+3.3 V) TERMINATE AT TRANSCEIVER INPUTS Z = 50 TDLVPECL TD+ 130 130 100 Z = 50 10 TD- o 9 TD+ o 8 N/C o 7 6 VCC TX o VEE TX o 1 H C2 VCC (+3.3 V) C3 10 F VCC (+3.3 V) TX o VCC RX o VEE RX o RD+ RX o RD- o SD 1 H C1 Z = 50 100 RDZ = 50 VCC (+3.3 V) 130 SD 82 RD+ 1 2 3 4 5 LVPECL 130 130 Z = 50 Note: C1 = C2 = C3 = 10 nF or 100 nF TERMINATE AT DEVICE INPUTS Figure 7. Recommended Decoupling and Termination Circuits 7 7 TERMINATE AT TRANSCEIVER INPUTS VCC (+3.3 V) PHY DEVICE VCC (+3.3 V) 10 nF 130 130 Z = 50 TD- Z = 50 LVPECL TD+ 10 9 8 7 6 82 82 VCC (+3.3 V) TD- o N/C o VEE TX o VCC TX o TD+ o TX 1 H C2 VCC (+3.3 V) C3 10 F 10 nF 130 130 RD+ VCC (+3.3 V) o VCC RX o VEE RX o SD o RD- o RD+ RX 1 H C1 1 2 3 4 5 Z = 50 VCC (+3.3 V) 10 nF Z = 50 130 SD 82 82 82 LVPECL RD- Z = 50 Note: C1 = C2 = C3 = 10 nF or 100 nF Figure 8. Alternative Termination Circuits O 1.4 0.1 (0.055 0.004) 7.11 (0.28) O 1.4 0.1 (0.055 0.004) 3.56 (0.14) TERMINATE AT DEVICE INPUTS Holes For Housing Leads O 1.4 0.1 (0.055 0.004) KEEP OUT AREA FOR PORT PLUG 7 (0.276) 10.8 (0.425) Spacing Of Front Housing Leads Holes 10.16 13.97 (0.4) (0.55) MIN. 13.34 7.59 (0.525) (0.299) 3.08 (0.121) 9.59 (0.378) 2 (0.079) 3 (0.118) 3 (0.118) 6 (0.236) 27 (1.063) 4.57 (0.18) 17.78 (0.7) 1.778 (0.07) 7.112 (0.28) O 2.29 (0.09) O 0.81 0.1 (0.032 0.004) 3.08 (0.121) DIMENSIONS IN MILLIMETERS (INCHES) NOTES: 1. THIS FIGURE DESCRIBES THE RECOMMENDED CIRCUIT BOARD LAYOUT FOR THE MT-RJ TRANSCEIVER PLACED AT .550 SPACING. 2. THE HATCHED AREAS ARE KEEP-OUT AREAS RESERVED FOR HOUSING STANDOFFS. NO METAL TRACES OR GROUND CONNECTION IN KEEP-OUT AREAS. 3. 10 PIN MODULE REQUIRES ONLY 16 PCB HOLES, INCLUDING 4 PACKAGE GROUNDING TAB HOLES CONNECTED TO SIGNAL GROUND. 4. THE SOLDER POSTS SHOULD BE SOLDERED TO CHASSIS GROUND FOR MECHANICAL INTEGRITY AND TO ENSURE FOOTPRINT COMPATIBILITY WITH OTHER SFF TRANSCEIVERS. Figure 9. Recommended Board Layout Hole Pattern 88 Regulatory Compliance Regulatory Compliance Transceiver Reliability and Performance Qualification Data The second case to consider is Electromagnetic Interference (EMI) static discharges to the x 5 transceivers have passed Avago reliability and These transceiver products are Most equipment designs These transceiver products are intended to enable comThe 2 exterior of the intended to designers to develop utilizing this high speed transmercial system enable commercialequipment that com- equipment performance qualification testing and are undergoing onchassis containinggoing quality and reliability monitoring. Details are availthe system the various international ceiver from Agilent will be plies withdesigners to develop regulations governing To from equipment that complies with required to meet the certification of Information Technologytransceiver See Equipment. parts. ablethe your Avago sales representative. requireextent that the the various international ments of FCC in the United the Regulatory Compliance Table for details. Additional MT-RJ connector is exposed to the Support Materials Applications regulations available from your Avago sales represenStates, CENELEC EN55022 information is governing certificaoutside of the equipment tion (CISPR 22) in Europe and tative.of Information Technology Avago Component Field Sales Office chassis it may be Contact your localVCCI in Japan. subject to Equipment. See the Regulatory for information on how to obtain evaluation boards for whatever ESD system level test Electrostatic Dischargefor details. Compliance Table (ESD) This the 2 x 5 transceivers. product is suitable for criteria that the equipment is Additional information is use in designs ranging from a There are two design cases in which immunity to ESD intended to meet. available from your Agilent Electromagnetic Interferencecomputer with a single desktop (EMI) damage is important. The first case is during handling of sales representative. Transceiver Reliability and transceiver to a concentrator the transceiver prior to mounting it on the circuit board. It Most equipment designs utilizing this high speed transPerformance Qualification Data or switch product with a large is important to use normal ESD handling precautions for Electrostatic Discharge (ESD) ceiver from Avago will be required to meet the requirenumber of transceivers. ESD sensitive devices. These pre-cautions include using The 2 x 5 transceivers have ments of FCC in the United States, CENELEC EN55022 There are two design cases in grounded wrist straps, work benches, and floorAgilent reliability and Europe and VCCI in Japan. This product is mats in passed (CISPR 22) in which immunity to ESD Immunity ESD controlled areas. The second case toperformance qualification for use in designs ranging from a desktop comconsider is static suitable damage is important. utilizing these discharges to the exterior of the equipment chassis con- undergoing a singleEquipmentto a concentrator or switch testing and are puter with transceiver The first transceiver parts. transceivers will be subject to taining the case is during To the extent that the MT- and reliabilitya large number of transceivers. ongoing quality product with handling of the transceiver radio-frequency RJ connector is exposed to the outside of the equipment monitoring. Details are availprior it mounting it on whatever ESD system your Agilent sales electromagnetic fields in some chassis to may be subject to the level able from Immunity circuit board. It equipment is environments. These test criteria that the is importantintended to meet. representative. Equipment utilizing these transceivers will be subject to to use normal ESD handling transceivers have a high Applications Support radio-frequency electromagnetic such fields. environMaterials precautions for ESD sensitive immunity to fields in some ments. These transceivers have a high immunity to such devices. These pre-cautions Contact your local Agilent fields. include using grounded wrist Component Field Sales Office straps, work benches, and floor for information on how to mats in ESD controlled areas. obtain evaluation boards for the 2 x 5 transceivers. Regulatory Compliance Table Feature Electrostatic Discharge (ESD) to the Electrical Pins Electrostatic Discharge (ESD) to the MT-RJ Receptacle Electromagnetic Interference (EMI) Immunity Test Method MIL-STD-883C Variation of IEC 801-2 FCC Class B CENELEC CEN55022 VCCI Class 2 Variation of IEC 61000-4-3 Performance Meets Class 2 (2000 to 3999 Volts). Withstand up to 2200 V applied between electrical pins. Typically withstand at least 25 kV without damage when the MT-RJ Connector Receptacle is contacted by a Human Body Model probe. Typically provide a 10 dB margin to the noted standards, however, it should be noted that final margin depends on the customer's board and chassis design. Typically show no measurable effect from a 10 V/m field swept from 10 to 450 MHz applied to the transceiver when mounted to a circuit card without a chassis enclosure. Compliant per Agilent testing under single fault conditions. TUV Certification: LED Class 1 Eye Safety AEL Class 1 EN60825-1 (+A11) 99 200 - TRANSMITTER OUTPUT OPTICAL SPECTRAL WIDTH (FWHM) - nm 10.8 0.1 (0.425 0.004) 3.8 (0.15) 1 (0.039) 9.8 0.1 (0.386 0.004) 180 1.0 160 3.0 1.5 140 2.0 2.5 3.0 tr/f - TRANSMITTER OUTPUT OPTICAL RISE/ FALL TIMES - ns 120 100 1260 1280 1300 1320 1340 1360 C - TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES - ns HFBR-5905 TRANSMITTER TEST RESULTS OF C, AND tr/f ARE CORRELATED AND COMPLY WITH THE ALLOWED SPECTRAL WIDTH AS A FUNCTION OF CENTER WAVELENGTH FOR VARIOUS RISE AND FALL TIMES. 13.97 (0.55) MIN. DIMENSIONS IN MILLIMETERS (INCHES) 0.25 0.1 (0.01 0.004) (TOP OF PCB TO BOTTOM OF OPENING) 14.79 (0.589) Figure 10. Recommended Panel Mounting Figure 11. Transmitter Output Optical Spectral Width (FWHM) vs. Transmitter Output Optical Center Wavelength and Rise/Fall Times. 6 RELATIVE INPUT OPTICAL POWER (dB) 5 4 3 2 1 0 -3 -2 -1 0 1 2 3 EYE SAMPLING TIME POSITION (ns) CONDITIONS: 1. T A = +25 C 2. V CC = 3.3 V dc 3. INPUT OPTICAL RISE/FALL TIMES = 1.0/2.1 ns. 4. INPUT OPTICAL POWER IS NORMALIZED TO CENTER OF DATA SYMBOL. 5. NOTE 15 AND 16 APPLY. Figure 12. Relative Input Optical Power vs. Eye Sampling Time Position. Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause catastrophic damage to the device. Limits apply to each parameter in isolation, all other parameters having values within the recommended operating conditions. It should not be assumed that limiting values of more than one parameter can be applied to the product at the same time. Exposure to the absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Storage Temperature Lead Soldering Temperature Lead Soldering Time Supply Voltage Data Input Voltage Differential Input Voltage (p-p) Output Current Symbol TS TSOLD tSOLD VCC VI VD IO Minimum Typical -40 Maximum Unit +100 +260 10 C C sec. V V V mA Reference -0.5 -0.5 3.6 VCC 2.0 50 Note 1 10 10 Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Data Input Voltage - Low Data Input Voltage - High Data and Signal Detect Output Load Differential Input Voltage (p-p) AFBR-5905 AFBR-5905A Symbol TA TA VCC VIL - VCC VIH - VCC RL VD Minimum Typical 0 -40 3.135 -1.810 -1.165 50 0.800 Maximum Unit +70 +85 3.465 -1.475 -0.880 C C V V V V Reference Note A Note B Note 2 Notes: A. Ambient Operating Temperature corresponds to transceiver case temperature of 0 C mininum to +85 C maximum with necessary airflow applied. Recommanded case temperature measurement point can be found in Figure 2. B. Ambient Operating Temperature corresponds to transceiver case temperature of -40 C mininum to +100 C maximum with necessary airflow applied. Recommanded case temperature measurement point can be found in Figure 2. Transmitter Electrical Characteristics AFBR-5905Z (TA= 0C to +70C, VCC=3.135V to 3.465V) AFBR-5905AZ (TA= -40C to +85C, VCC= 3.135V to 3.465V) Parameter Supply Current Power Dissipation Data Input Current - Low Data Input Current - High Symbol ICC PDISS IIL IIH Minimum Typical 133 0.45 -350 -2 18 Maximum Unit 175 0.60 350 mA W A A Reference Note 3 Note 5a Receiver Electrical Characteristics AFBR-5905Z (TA= 0C to +70C, VCC= 3.135V to 3.465V) AFBR-5905AZ(TA= -40C to +85C, VCC= 3.135V to 3.465V) Parameter Supply Current Power Dissipation Data Output Voltage - Low Data Output Voltage - High Data Output Rise Time Data Output Fall Time Signal Detect Output Voltage - Low Signal Detect Output Voltage - High Signal Detect Output Rise Time Signal Detect Output Fall Time Power Supply Noise Rejection Symbol ICC PDISS VOL - VCC VOH - VCC tr tf VOL - VCC VOH - VCC tr tf PSNR Minimum Typical 65 0.225 -1.83 -1.085 0.35 0.35 -1.83 -1.085 0.35 0.35 50 Maximum Unit 120 0.415 -1.55 -0.88 2.2 2.2 -1.55 -0.88 2.2 2.2 mA W V V ns ns V V ns ns mV Reference Note 4 Note 5b Note 6 Note 6 Note 7 Note 7 Note 6 Note 6 Note 7 Note 7 11 11 Transmitter Optical Characteristics AFBR-5905Z (TA= 0C to +70C, VCC= 3.135V to 3.465V) AFBR-5905AZ (TA= -40C to +85C, VCC= 3.135V to 3.465V) Parameter Output Optical Power 62.5/125 m, NA = 0.275 Fiber Output Optical Power 50/125 m, NA = 0.20 Fiber Optical Extinction Ratio Output Optical Power at Logic Low "0" State Center Wavelength Spectral Width - FWHM - RMS Optical Rise Time Optical Fall Time Systematic Jitter Contributed by the Transmitter Random Jitter Contributed by the Transmitter BOL EOL BOL EOL Symbol PO PO Minimum Typical -19 -20 -22.5 -23.5 10 -15.7 -20.3 Maximum Unit -14 -14 dBm avg dBm avg dB -45 dBm avg nm nm 3.0 3.0 1.2 0.52 ns ns ns p-p ns p-p Reference Note 8 Note 8 Note 9 Note 10 Note 23 Figure 11 Note 23 Figure 11 Note 12, 23 Figure 11 Note 12, 23 Figure 11 Note 13 Note 14 PO ("0") C tr tf SJ RJ 0.6 0.6 1270 1308 147 63 1.2 2.0 0.21 0.14 1380 Receiver Optical and Electrical Characteristics AFBR-5905Z (TA= 0C to +70C, VCC= 3.135V to 3.465V) AFBR-5905AZ (TA= -40C to +85C, VCC= 3.135V to 3.465V) Parameter Input Optical Power Minimum at Window Edge Input Optical Power Minimum at Eye Center Input Optical Power Maximum Operating Wavelength Systematic Jitter Contributed by the Receiver Random Jitter Contributed by the Receiver Signal Detect - Asserted Signal Detect - Deasserted Signal Detect - Hysteresis Signal Detect Assert Time (off to on) Signal Detect Deassert Time (on to off) Symbol PIN Min (W) PIN Min (C) PIN Max SJ RJ PA PD PA - PD Minimum Typical Maximum Unit -30 -31 dBm avg dBm avg dBm avg 1380 nm ns p-p ns p-p dBm avg dBm avg dB Reference Note 15 Figure 12 Note 16 Figure 12 Note 15 Note 17 Note 18 Note 19 Note 20 Note 21 Note 22 -14 1270 0.15 0.11 PD + 1.5 dB -45 1.5 0 0 2 5 100 350 1.2 1.91 -31 s s 12 12 Notes: 1. This is the maximum voltage that can be applied across the Differential Transmitter Data Inputs to prevent damage to the input ESD protection circuit. 2. The outputs are terminated with 50 connected to VCC -2 V. 3. The power supply current needed to operate the transmitter is provided to differential ECL circuitry. This circuitry maintains a nearly constant current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated and conducted or emitted to neighboring circuitry. 4. This value is measured with the outputs terminated into 50 connected to VCC - 2 V and an Input Optical Power level of -14 dBm average. 5a. The power dissipation of the transmitter is calculated as the sum of the products of supply voltage and current. 5b. The power dissipation of the receiver is calculated as the sum of the products of supply voltage and currents, minus the sum of the products of the output voltages and currents. 6. This value is measured with respect to VCC with the output terminated into 50 connected to VCC - 2 V. 7. The output rise and fall times are measured between 20% and 80% levels with the output connected to VCC -2 V through 50 . 8. These optical power values are measured with the following conditions: * The Beginning of Life (BOL) to the End of Life (EOL) optical power degradation is typically 1.5 dB per the industry convention for long wavelength LEDs. The actual degradation observed in Avago's 1300 nm LED products is < 1 dB, as specified in this data sheet. * Over the specified operating voltage and temperature ranges. * With 25 MBd (12.5 MHz square-wave), input signal. * At the end of one meter of noted optical fiber with cladding modes removed. The average power value can be converted to a peak power value by adding 3 dB. Higher output optical power transmitters are available on special request. Please consult with your local Avago sales representative for further details. 9. The Extinction Ratio is a measure of the modulation depth of the optical signal. The data "1" output optical power is compared to the data "0" peak output optical power and expressed in decibels. With the transmitter driven by a 25 MBd (12.5 MHz square-wave) input signal, the average optical power is measured. The data "1" peak power is then calculated by adding 3 dB to the measured average optical power. The data "0" output optical power is found by measuring the optical power when the transmitter is driven by a logic "0" input. The extinction ratio is the ratio of the optical power at the "1" level compared to the optical power at the "0" level expressed in decibels. 10. The transmitter will provide this low level of Output Optical Power when driven by a logic "0" input. This can be useful in link troubleshooting. 11. The relationship between Full Width Half Maximum and RMS values for Spectral Width is derived from the assumption of a Gaussian shaped spectrum which results in a 2.35 X RMS = FWHM relationship. 12. The optical rise and fall times are measured from 10% to 90% when the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input signal. The ANSI T1E1.2 committee has designated the possibility of defining an eye pattern mask for the transmitter optical output as an item for further study. Avago will incorporate this requirement into the specifications for these products if it is defined. The HFBR5905 products typically comply with the template requirements of CCITT (now ITU-T) G.957 Section 3.2.5, Figure 2 for the STM-1 rate, excluding the optical receiver filter normally associated with single mode fiber measurements which is the likely source for the ANSI T1E1.2 committee to follow in this matter. 13. Systematic Jitter contributed by the transmitter is defined as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square-wave), 27 - 1 psuedorandom data pattern input signal. 14. Random Jitter contributed by the transmitter is specified with a 155.52 MBd (77.5 MHz square-wave) input signal. 15. This specification is intended to indicate the performance of the receiver section of the transceiver when Input Optical Power signal characteristics are present per the following definitions. The Input Optical Power dynamic range from the minimum level (with a window time-width) to the maximum level is the range over which the receiver is guaranteed to provide output data with a Bit Error Rate (BER) better than or equal to 1 x 10-10. * At the Beginning of Life (BOL) * Over the specified operating temperature and voltage ranges * Input is a 155.52 MBd, 223 - 1 PRBS data pattern with 72 "1"s and 72 "0"s inserted per the CCITT (now ITU-T) recommendation G.958 Appendix I. * Receiver data window time-width is 1.23 ns or greater for the clock recovery circuit to operate in. The actual test data window time-width is set to simulate the effect of worst case optical input jitter based on the transmitter jitter values from the specification tables. The test window time-width is AFBR-5905Z 3.32 ns. * Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave, input signal to simulate any cross-talk present between the transmitter and receiver sections of the transceiver. 16. All conditions of Note 15 apply except that the measurement is made at the center of the symbol with no window time-width. 17. Systematic Jitter contributed by the receiver is defined as the combination of Duty Cycle Distortion and Data Dependent Jitter. Systematic Jitter is measured at 50% threshold using a 155.52 MBd (77.5 MHz square-wave), 27 - 1 psuedorandom data pattern input signal. 18. Random Jitter contributed by the receiver is specified with a 155.52 MBd (77.5 MHz square-wave) input signal. 19. This value is measured during the transition from low to high levels of input optical power. 20. This value is measured during the transition from high to low levels of input optical power. At Signal Detect Deassert, the receiver outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively. 21. The Signal Detect output shall be asserted within 100 s after a step increase of the Input Optical Power. 22. Signal detect output shall be de-asserted within 350 s after a step decrease in the Input Optical Power. At Signal Detect Deassert, the receiver outputs Data Out and Data Out Bar go to steady PECL levels High and Low respectively. 23. The AFBR-5905Z transceiver complies with the requirements for the trade-offs between center wavelength, spectral width, and rise/ fall times shown in Figure 11. This figure is derived from the FDDI PMD standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the description in ANSI T1E1.2 Revision 3. The interpretation of this figure is that values of Center Wavelength and Spectral Width must lie along the appropriate Optical Rise/ Fall Time curve. For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries. Data subject to change. Copyright (c) 2008 Avago Technologies Limited. All rights reserved. 5989-3083EN - February 20, 2008 |
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